gdp's Comments

FPGA Simulation : SystemVerilog Code Examples

Sun, 31 Mar 2013 15:44:36 +0000

Hi Ram, I answered your question on this page: http://www.fpgasimulation.com/?page_id=2 Ray

FPGA Simulation : About Us

Thu, 28 Mar 2013 03:45:05 +0000

Hi Ram, There are two ways to do this with SystemVerilog: 1. You can hierarchically reference the result (top.dut.tinyalu.result) 2. You can use a bind command to "instantiate" a monitoring module in the hierarchy. If you had a module such as monitor_result monitor_result_i (result); And if your tinyalu were in top.dut. you could do bind top.dut monitor_result monitor_result_i(result) Both of these solutions do not require you to touch the DUT code. VHDL 2008 added hierarchical references to VHDL.

FPGA Simulation : SystemVerilog Code Examples

Thu, 2 Aug 2012 12:51:15 +0000

I believe he's talking about FPGA SIMULATION (link to the right).

FPGA Simulation : SystemVerilog Code Examples

Fri, 15 Jul 2011 20:17:32 +0000

Hi Sudipta, When you say "showing 2 error" what do you mean? Ray

FPGA Simulation : FPGA Simulation Errata

Thu, 19 May 2011 13:32:46 +0000

Hi Liu, I have posted a solution to the IUS problem: http://www.fpgasimulation.com/?page_id=155

FPGA Simulation : FPGA Simulation Errata

Thu, 19 May 2011 13:12:04 +0000

Hi Liu, You're the second person to mention this problem with IUS. There is probably a very ugly way to do this. Let me give it a little thought. I suspect that you can create a variable inside the module that holds the TLM fifo and then use Verilog hierarchical references to set the variable to the TLM fifo. Also, be sure to tell your Cadence FAE that this has made a Mentor FAE very happy. That should motivate them to fix it faster :-) Ray

FPGA Simulation : FPGA Simulation Errata

Mon, 16 May 2011 13:48:56 +0000

Hi Liu, I'm not certain what you mean in your message. Do you mean the report looks different? I wonder if OVM has changed since then. Ray

Naked Security : Death by PowerPoint? Kama Sutra presentation leads to backdoor infection

Wed, 12 Jan 2011 12:47:38 +0000

May I snigger now? The headline is just too funny.

FPGA Simulation : More Lectures from FPGA Simulation online

Thu, 1 Jul 2010 03:40:32 +0000

Hi Aiken, I've uploaded an example to the SystemVerilog Code Examples page. You can see the tab to the examples page at the top of this page.

FPGA Simulation : FPGA Simulation Errata

Wed, 7 Apr 2010 17:37:24 +0000

Wow. You're right. There's an errata on the errata. How recursive! I've fixed it.